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71.
通过对线间电容耦合模型的研究, 提出了一种基于互连线电容耦合的SR锁存电路设计方案. 该方案首先分析互连线间电容耦合关系, 利用MOS管栅极电容模拟互连线电容; 然后利用电容耦合结构与线计算特性, 设计或非逻辑门电路, 在此基础上实现基于互连线电容耦合的SR锁存电路; 最后在TSMC 65nm Spectre环境下仿真验证. 结果表明 所设计的电路逻辑功能正 确, 且具有低硬件开销特性. 相似文献
72.
《Physics letters. A》2020,384(1):126039
Different from the conventional Rydberg antiblockade (RAB) regime that either requires weak Rydberg-Rydberg interaction (RRI), or compensates the RRI-induced energy shift by introducing off-resonant interactions, we show that RAB regime can be achieved by resonantly driving the transitions between ground state and Rydberg state under strong RRI. The Rabi frequencies are of small amplitude and time-dependent harmonic oscillation, which plays a critical role for the presented RAB. The proposed unconventional RAB regime is used to construct high-fidelity controlled-Z (CZ) gate and controlled-not (CNOT) gate in one step. Each atom requires single external driving. And the atomic addressability is not required for the presented unconventional RAB, which would simplify experimental complexity and reduce resource consumption. 相似文献
73.
74.
Three novel perylene derivatives were prepared by introducing two phenyl (biphenyl or naphthyl)-bridging cholesterol units on bay positions and six alkyl chains on imides positions. The influences of different bay-bridging spacers on mesomorphic properties and photophysical properties were investigated. They presented the ordered hexagonal columnar liquid crystalline behaviours, although the large aromatic spacers were bridged on the bay positions. The mesomorphic and photophysical properties could be tuned effectively by the structures of spacers on bay positions. The larger and more rigid aromatic spacer on bay positions resulted in higher phase transition temperatures and stronger fluorescence emission. 相似文献
75.
介绍了一种具有高阈值电压和大栅压摆幅的常关型槽栅AlGaN/GaN金属氧化物半导体高电子迁移率晶体管。采用原子层淀积(ALD)方法实现Al2O3栅介质的沉积。槽栅常关型AlGaN/GaN MOS-HEMT的栅长(Lg)为2 μm,栅宽(Wg)为0.9 mm(0.45 mm×2),栅极和源极(Lgs)之间的距离为5 μm,栅极和漏极(Lgd)之间的距离为10 μm。在栅压为-20 V时,槽栅常关型AlGaN/GaN MOS-HEMT的栅漏电仅为0.65 nA。在栅压为+12 V时,槽栅常关型AlGaN/GaN MOS-HEMT的栅漏电为225 nA。器件的栅压摆幅为-20~+12 V。在栅压Vgs=+10 V时,槽栅常关型AlGaN/GaN MOS-HEMT电流和饱和电流密度分别达到了98 mA和108 mA/mm (Wg=0.9 mm), 特征导通电阻为4 mΩ·cm2。槽栅常关型AlGaN/GaN MOS-HEMT的阈值电压为+4.6 V,开启与关断电流比达到了5×108。当Vds=7 V时,器件的峰值跨导为42 mS/mm (Wg=0.9 mm,Vgs=+10 V)。在Vgs=0 V时,栅漏间距为10 μm的槽栅常关型AlGaN/GaN MOS-HEMT的关断击穿电压为450 V,关断泄露电流为0.025 mA/mm。 相似文献
76.
A scheme to implement the controlled‐NOT (CNOT) gate for quantum systems is proposed, which is based on Lyapunov control. The scheme does not require precise control of the interaction time since the system is stable when the control fields vanish. In particular, the control fields can be easily obtained by most initial states. As an example, the CNOT gate is realized for two atoms trapped in an optical cavity by exploiting two disturbance cases. Compared to continuous disturbance, the fidelity of the CNOT gate is higher under impulsive disturbance, however, interaction times are much longer. Numerical simulations indicate that the scheme is robust against variations of control parameters and decoherence caused by atomic spontaneous emission and cavity decay. Therefore, the scheme may provide useful applications in quantum computation. 相似文献
77.
You-Ji Fan Zhen-Fei Zheng Yu Zhang Dao-Ming Lu Chui-Ping Yang 《Frontiers of Physics》2019,14(2):21602
We propose a single-step implementation of a muti-target-qubit controlled phase gate with one catstate qubit (cqubit) simultaneously controlling n–1 target cqubits. The two logic states of a cqubit are represented by two orthogonal cat states of a single cavity mode. In this proposal, the gate is implemented with n microwave cavities coupled to a superconducting transmon qutrit. Because the qutrit remains in the ground state during the gate operation, decoherence caused due to the qutrit’s energy relaxation and dephasing is greatly suppressed. The gate implementation is quite simple because only a single-step operation is needed and neither classical pulse nor measurement is required. Numerical simulations demonstrate that high-fidelity realization of a controlled phase gate with one cqubit simultaneously controlling two target cqubits is feasible with present circuit QED technology. This proposal can be extended to a wide range of physical systems to realize the proposed gate, such as multiple microwave or optical cavities coupled to a natural or artificial three-level atom. 相似文献
78.
弧形泄水闸是水利枢纽工程中常见的挡水、泄水建筑物,其在关闭或开启过程中或者局部开启运行时,在水流脉动压力作用下会产生振动,容易引起闸门结构破坏。本文针对边孔闸门与中孔闸门不同的水流边界条件特点,制作了带导流墙与无导流墙两个弧形闸门模型。在实验室内开展了不同库水位、不同闸门开度下的物理模型试验,并对两个模型上大量测点的水流脉动压力数据进行比较分析。试验表明,导流墙的存在对脉动压力主频的影响较小,但对脉动压力均方根值影响较大;在较高库水位下相对开度位于0.2至0.3区间内时,导流墙的存在不但不会改善闸门的受力状况,反而还会导致受力增强。 相似文献
79.
We propose an efficient method to construct an optical four-photon |χ> state analyzer via the cross-Kerr nonlinearity combined with linear optical elements. In this protocol, two four-qubit parity-check gates and two controlled phase gates are employed. We show that all the 16 orthogonal four-qubit |χ> states can be completely discriminated with our apparatus. The scheme is feasible and realizable with current technology. It may have useful potential applications in quantum information processing which based on |χ> state. 相似文献
80.
Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays(FPGAs), FPGA time-to-digital converters(TDCs) have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold(TOT) measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC's integrity.This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method,TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15 ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates. 相似文献